1. Field of Invention
The present invention relates to an integrated circuit. More particularly, the present invention relates to an interconnection structure of a chip.
2. Description of Related Art
An integrated circuit is formed by shrinking many kinds of electronic circuits and lines into a chip, and uses a power bus to provide power needed by the foregoing electronic circuits.
FIG. 1 illustrates a schematic view of a conventional power delivering structure of a chip. As illustrated in FIG. 1, power rings 104a and 104b around a chip 100 are regarded as a power bus of the chip 100, and are connected to pad 102a and 102b, respectively, for providing different voltages. The voltage of the pad 102a is high (VDD), and the voltage of the pad 102b is low (VSS). Moreover, several power lines 106a and 106b are parallel in the core of the chip 100, and are connected to the power ring 104a and 104b, respectively, for uniformly delivering power to electronic circuits in the core of the chip (not illustrated in the figure).
However, this conventional power delivering structure has the following disadvantages:
1. The power rings are too large and waste valuable and limited space in the chip. A typical width of the conventional power ring is between about 20 and 40 micrometers. If the width of the power ring is reduced, a voltage drop caused by the reduced width makes the operating voltage reduction, and/or some internal electronic circuits operate under the rated voltage. A typical area of an integrated circuit is about 9000000 square micrometers, and if a width of a power ring around the integrated circuit is 30 micrometers, the power ring occupies about 7% of the area of the integrated circuit. This is very wasteful of the valuable and limited area of the chip.
2. The power delivering of the internal electronic circuits is limited in a pre-determined route, which cannot supply power flexibly. Moreover, if certain electronic circuits in the delivering route consume too much electric power, a voltage drop occurs, and the voltage supplying for other electronic circuits is therefore degraded. In addition, as illustrated in FIG. 1, the power delivering structure delivers electric power to the electronic circuits with a long and narrow power line, and if the chip is very large, a power distribution uniformity issue easily occurs and affects the chip performance.